Consider the following makefile:

my_program: my_program.c
	echo Starting to compile my_program ...
	cc my_program.c -o my_program
	echo done.

Running this makefile produces the following:

echo Starting to compile my_program ...
Starting to compile my_program ...
cc my_program.c -o my_program
echo done.
done.

The make program, by default, announces commands as it executes them. However, you can suppress this by prepending an @ character to a command. For example, if you change the above makefile to the following:

my_program: my_program.c
	@echo Starting to compile my_program ...
	cc my_program.c -o my_program
	@echo done.

Then you will get the following, more pleasant output:

Starting to compile my_program ...
cc my_program.c -o my_program
done.

Rewrite rules

In a large makefile, you may have something like the following:

file_1.o: file_1.c
	cc -g -c file_1.c

file_2.o: file_2.c
	cc -g -c file_2.c

file_3.o: file_3.c
	cc -g -c file_3.c

file_4.o: file_4.c
	cc -g -c file_4.c

...

You're doing the same thing for every file, so it seems tedious to have to write that down for each file. You might rather have a rule that says, for any file with a .c extension, to create a file with a .o extension, run the cc -c command with that file name as an argument. The way to do this is:

.c.o:
	cc -c -g $<